1. Field of the Invention
The embodiments of the invention generally relate to on-chip repair of semiconductor devices and, more particularly, to a design structure for semiconductor chip structure and a method that incorporate a localized, on-chip, repair scheme for devices that exhibit performance degradation as a result of negative bias temperature instability (NBTI).
2. Description of the Related Art
Negative bias temperature instability (NBTI) is a phenomenon in which powered-up sub-micron complementary metal oxide semiconductor (CMOS) devices and, more specifically, p-type field effect transistors (PFETs), exhibit performance degradation over time and/or under certain use conditions. This NBTI primarily causes an increase in the PFET threshold voltage and, thereby causes a reduction in the PFET drive current. Consequently, there is a need in the art for semiconductor chip structure and a method that allows for localized, on-chip, repair of devices suffering from NBTI performance degradation.